1. Field of the Invention.
This invention relates to the field of metal-oxide-semiconductor manufacturing. More particularly this invention discloses a process for forming graded junctions for source and drain regions.
2. Prior Art.
In forming metal oxide semiconductor field effect transistors (MOSFET) a variety of problems exist as artifacts of the processing sequence. A high concentration of impurities is needed in the source and drain regions in the body of the semiconductor in order (1) to make good electrical contact from the metallic interface to the source/drain regions and (2) to decrease the resistivity of the source and drain regions and thereby increase the MOSFET performance characteristics. However, a small concentration of impurities in the source and drain regions is needed in order to prevent the injection of hot electrons that become trapped in the insulating layer between the gate electrode member and the semiconductor body causing degradation in threshold voltage characteristics. These competing requirements for source and drain region impurity concentrations have caused engineers to develop complex process sequences which are difficult to manufacture and achieve inconsistent results.
Ion implantation is one technique for introducing impurities into the substrate to form source and drain regions. In the field of predepositing impurities through ion implantation, a phenomenon known as channeling has been observed. Channeling is a condition where a significant portion of the implanted ions will pass through the inherent voids between atomic planes in the semiconductor crystal when the ion beam is oriented parallel to the crystal planes. This allows those channeled ions to come to rest in a location considerably deeper in the semiconductor body than desired. The depth of the ions in a semiconductor crystal after an implantation step where channeling has occurred is difficult to control. This is particularly true for ions such as phosphorus and boron.
In manufacturing MOSFETs shallow junctions for the source and drain regions are desired in the regions immediately adjacent to the region under the gate electrode member. This is because the source to drain punch through voltage decreases as junction depth increases. Thus, source and drain junctions that are formed after the ions have been predeposited in the semiconductor substrate through ion implantation in such a manner that channeling can occur are at an uncontrollable depth and generally have a low punch through voltage.
In order to counteract the effects of channeling the substrate crystal planes are skewed from parallel with respect to the ion beam and thereby form shallow junctions for the source and drain regions. By so doing the ions within the beam are not propelled in the path substantially parallel to one of the semiconductor crystal channels. Thus, the ions must strike an atom of the semiconductor crystal near the surface and come to rest within a short distance of the surface of the semiconductor substrate.
It is desirable in manufacturing MOSFETs that each individual MOSFET be formed such that the source and drain regions are substantially symmetrical one to the other. Implanting at an angle which will avoid channeling and thereby improve the punchthrough voltage characteristics of individual MOSFETs will also form a MOSFET in which the source or drain regions are asymmetrical and can thus adversely affect the performance characteristics of that device. Ion implantation machines typically used in manufacturing integrated circuits allow the wafers to be placed on the implantation chuck with random orientation. This random orientation operating in conjunction with an angled implant further compounds the manufacturing problem for MOSFETs by forming an inconsistent amount of asymmetry from one wafer to the next.
A variety of process flows have been applied in order to manufacture consistent MOSFET devices. The earliest MOSFET devices were formed by first diffusing into the source and drain regions and then defining the gate. This had the obvious disadvantage of requiring two critical mask steps. In forming MOSFETs for which the gate member was defined subsequent to the source and drain required significant gate overlap in order to ensure that the gate adequately covered the entire channel. The first major advance was to use the polysilicon gate electrode member as a diffusion mask for the source and drain regions (U.S. Pat. No. 3,475,234). This allowed the designer to manufacture a transistor with a minimum overlap by eliminating the need for mask alignment tolerance in the gate dimension with respect to the channel length.
The next advance was to use the gate member as a mask to implantation (U.S. Pat. No. 3,481,030). The major advantage of this technique was that the dose could be accurately controlled and the amount of gate to source and drain region overlap could be kept at a minimum. However, two new problems were created by this technique.
The process of ion implantation or bombardment created damage to the semiconductor substrate. This damage could only be corrected through subsequent high temperature processing known as annealing. The temperatures required to perform this anneal step in the semiconductor body would melt aluminum. Thus, the use of an aluminum gate was essentially precluded (U.S. Pat. No. 3,472,712).
Another problem that occurred resulted from hot electron trapping. This problem is solved if the concentration of dopants within the source and drain regions changed gradually over the distance in the region adjacent to the source and drain junctions. Then, the electrons making the transition across the junction do not accelerate to high velocities. Without sufficient high energy electrons in the channel regions, electrons do not have sufficient energy to enter the gate electrode insulator.
Many techniques have been tried to form graded junctions. One such technique involved the use of a masking layer on top of the gate electrode structure which overhung the edges of the gate electrode member (U.S. Pat. No. 4,198,250). This structure is typically manufactured by first forming the gate electrode insulating layer, then forming a layer of the gate electrode material and lastly forming another layer used as a mask. The masking layer is etched with ordinary photomasking techniques. The gate electrode member is selectively wet etched and then overetched such that it undercuts the overlying masking layer.
Next the device is ion implanted at a sufficient energy to allow the implanted ions to penetrate the masking layer overhang. However, only a portion of those implanted ions penetrating the overhang penetrate the gate electrode insulating area and enter the underlying substrate material. Thus, the substrate underneath the masking layer overhang has a lower dopant concentration than the substrate not underneath the masking layer. Following this ion implantation with a high temperature anneal step repairs damage to the substrate and activates the dopant species.
Another similar technique is to form the same structure as previously described with the overhanging masking layer. Here the source and drain dopants are introduced with two ion implantation steps. The first implant is performed at a low energy and relatively high dose. The overhanging masking layer is then removed. The second implant is performed at a low energy and a low dose. The doping concentration in the substrate immediately adjacent the region under the gate member is relatively small. The doping concentration in the substrate spaced laterally away from the region under the gate member by the distance of the overhanging masking layer is relatively large. After annealing, a graded junction MOSFET is formed. The disadvantage of these two techniques is that very precise control is required over the etching time of the gate electrode member material. It is difficult to obtain consistent results for the length of the graded section of the source and drain junctions from one manufacturing lot to another.
Another technique is to form the insulated gate electrode member then implant two different species of the same conductivity type in the source and drain regions adjacent to region under the gate. The dopant species for this technique is selected from dopants having different diffusion constants. Then, the annealing steps used to repair crystal damage and activate the doping species will drive the faster diffusing species further. This forms a graded junction. Unfortunately, this technique is self limiting. Diffusivity of the semiconductor dopants is a function not only of the diffusion constant for each species, but is also a function of the doping concentration. Because of this the graded region will typically be shorter than can be obtained with other techniques and because the slow diffusing species will always underlap the gate, the gate aided breakdown voltages cannot be beneficial with this approach.
Another technique to form graded junctions is to first form the gate electrode member and then to deposit a uniform masking layer over the structure. By performing anisotropic etch on this masking layer, spacers composed of masking material are left behind on the vertical sidewalls of the gate electrode member. Next a heavy dose source and drain region implant is performed on the structure with the sidewall spacers. The sidewall spacers prevent these implanted ions from reaching the substrate. This heavy dose implant will form implanted regions in the substrate laterally spaced apart from the gate member on the structure with the sidewall spacers. The sidewall spacers are then removed by a selective etch. This is followed by a low dose implant to form the low concentration portion of the graded source and drain junctions. This technique had the advantage over the previous methods in that the length of the low dose regions can be more accurately controlled than with the overhanging structure described above due to the fact that the thickness of the masking layer is more easily controlled. Because of this advantage and the ability to develop tighter processing controls, smaller and smaller device sizes are possible. However, this process sequence recreates two old problems. The lightly doped implant must either (1) be performed at a small angle in order to avoid channeling and form a shallow junction which of necessity forms inconsistent and asymmetric MOSFETs thereby creating manufacturing and design problems or (2) if the implant is performed in a substantially vertical manner inconsistent junction depths are obtained. Deep source and drain junctions also causes a decrease in punch through voltage. As the punch through voltage decreases the range of acceptable operating voltages is diminished, thereby reducing applications available to the user of the MOSFET. Thus, an improved method for forming MOSFETs with graded junctions was needed.